Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
There is a constant need to shrink the size of the memory cell arrays in order to maximize the number of memory cells on a single wafer. It is well known that forming memory cells in pairs, with each pair sharing a single source region, and with adjacent pairs of cells sharing a common drain region, reduces the size of the memory cell array. However, a large area of the array is typically reserved for the bit-line connection to the drain regions. The bit-line area is often occupied by the contact openings between memory cell pairs, and the contact to wordline spacing, which strongly depends upon lithography generation, contact alignment and contact integrity. In addition, significant space is reserved for the word-line transistor, the size of which is set by lithography generation and junction scaling.
Traditionally, floating gates are formed with a sharp edge facing a control gate to enhance Fowler-Nordheim tunneling, which is used to move electrons off of the floating gate during an erase operation. The sharp edge is typically formed by oxidizing or partially etching the top surface of the floating gate poly in an uneven manner. In order to enhance the oxidation process, the floating gate poly is typically lightly doped to avoid the formation of large grains. However, as the dimensions of the floating gate get smaller, the grains of the polysilicon (which are enlarged due to the thermal cycles of the oxidation process) become significant in size compared to the overall size of the floating gate. The large grain size relative to the size of the floating gate causes the sharp edge to be unevenly formed, which compromises the operation and functionality of the floating gate.
There is also a need to improve the programming efficiency of memory cell array. FIG. 1 illustrates a well known split-gate non-volatile memory cell design, that includes a floating gate 1 and a control gate 2 that are insulated from each other by an insulation material 3 and are formed over a substrate 4. A source region 5 and a drain region 6 are formed in the substrate 4, with a channel region therebetween. In conventional programming schemes, the electrons in the channel region flow from the drain 6 to the source 5 in a path parallel to the floating gate 1, where a relatively small number of the heated electrons are injected onto the floating gate 1. The estimated program efficiency (number of electrons injected compared to total number of electrons) is estimated at about 1/1000.
There is also a need to increase the erasing efficiency and reliability of the memory cell array. To erase the memory cell shown in FIG. 1, the electric potential of the control gate 2 is increased until electrons on the floating gate 1 tunnel from a sharp tip 7 of the floating gate 1 through the insulation material 3 and onto the control gate 2 via Fowler-Nordheim tunneling. However, the electric field lines 8 between the floating gate tip 7 and the adjacent control gate surface 9 are asymmetric, with a much stronger electric field line density near the floating gate tip 7 compared to that near the control gate surface 9. Defects and oxide degradation from excessive electric fields tend to occur in the insulation material 3 where the electric field line density is the greatest. Thus, the asymmetric electric field line density near the floating gate tip 7 limits the maximum voltages usable to erase the memory cells, and limits the scalability of the memory cell size.
There is a need for a non-volatile, floating gate type memory cell array with significant cell size reduction while providing enhanced programming and erase efficiency and memory cell reliability.